Ziao Wang

University of California, Santa Barbara

Master of Science in Computer Science • 2023 — Present

Tsinghua University

Bachelor of Engineering, Computer Science and Technology • 2019 — 2023

• Shenzhen Stock Exchange Scholarship for Academic Excellence (2021)
• Member of the (departmental) Student's Association of Science and Technology (2020~2021)

Benchmarking PINNs

Group member • February 2023 — August 2023

• Creates the benchmarking toolbox "PINNacle" that helps provide a comprehensive comparison between different PINN methods across PDEs representing different physical scenarios
• Contributed to project by implementing the part of the toolbox that tests domain decomposition methods in PINNs
• Check out our source code and preprint here!

Resilience in Science

Student Research Intern (advised by Kristina Lerman, collaborated with Kian Ahrabian) • June, 2022 — Sep, 2022

• Identified the pandemic's impact to the output, participation and collaboration of the scientific community by constructing collaboration networks from bibliographic datasets and analyzing metrics of network science

User Privacy in the Prompt Learning Paradigm

Research Assistant (advised by Zhiyuan Liu, collaborated with Ganqu Cui) • Sept, 2021 — May, 2022

• Demonstrated that deep learning models with prompt learning do not leak more sensitive information than those with fine-tuning, and attack methods with prompt learning can not extract more sensitive information than baselines
• Research is done by conducting demonstration experiments of extracting private user information under the prompt learning paradigm of NLP

Implementation of a Pipelined RISCV CPU

Group Project for Computer Organization 2021 Fall, Tsinghua University • Nov, 2021

Correctly implemented the digital logic for exceptional control flow and memory address translation as specified by the RISCV manual.

Image Renderer based on Path Tracing

Course Project for Fundamentals of Computer Graphics 2021 Spring, Tsinghua University • June, 2021

• Implemented features for a renderer, including texture mapping, parametric surfaces, depth of field and bounding box acceleration of complex meshes.
• Code is based on a framework provided by the course TAs, but path tracing and the above features are implemented individually.

Packet Sniffer on FPGA

Group Project for Digital Logic Design 2021 Spring, Tsinghua University • April, 2021; June, 2021

• Created a packet sniffer able to list information about passing packets, based on a Xilinx FPGA board with Ethernet and VGA interface
• I utilized an open source Verilog library in my code to extract and pass on relevant information from the Ethernet interface.

Programming Languages

Proficient in C, C++, and Python

Frameworks and Libraries

Pytorch, OpenMP, OpenMPI

Other Programmer Skills

Experience with Git, Linux shell and remote servers

Languages

Mandarin (native) and English (110 in the TOEFL iBT test)